In recent years, with an increase in integration, function, and speed of semiconductor integrated circuit devices, three-dimensional integration techniques by chip-on-chip, chip-on-wafer, or wafer-on-wafer packaging of substrates using through electrodes have been suggested. (See, for example, ITRS (The International Technology Roadmap for Semiconductors) 2007, Assembly and Packaging Chapter (Japanese Language Edition), pp.41-42.)
This is because, in conventional two-dimensional miniaturization such as system-on-chip (SoC), degradation in performance is concerned, which is caused by a rise in the interconnection resistance due to grain boundary scattering and interface scattering of electrons with reduction in the cross-sectional areas of interconnects, and an increase in interconnection delays due to an increase in interconnect length.
Thus, in three-dimensional integration techniques, semiconductor integrated circuit devices are three-dimensionally stacked to increase areas capable of interconnection, thereby increasing the cross-sectional areas of the interconnects and reducing the interconnect length. That is, integration is accelerated and performance is improved.
In three-dimensional integration techniques, where substrates such as silicon substrates are stacked, metal electrodes are heated and compression-bonded using, for example, solder bumps etc. for electrical interconnection between the substrates in chip-on-chip, chip-on-wafer, or wafer-on-wafer packaging.
FIGS. 3A and 3B are cross-sectional views illustrating steps of electrode bonding in a conventional three-dimensional integration technique.
First, as shown in FIG. 3A, a substrate 11 having electrode pads 12 on its surface, and a substrate 21 having electrode pads 22 on its surface are prepared. Then, solder bumps 13 melting at a low temperature are formed on the electrode pads 12. After that, the substrate 11 and the substrate 21 are arranged so that the solder bumps 13 on the electrode pads 12 face the electrode pads 22. The solder bumps 13 may be made of, for example, an alloy containing tin.
Next, as shown in FIG. 3B, the solder bumps 13 on the electrode pads 12 are compression-bonded to the electrode pads 22, and then, the solder bumps 13 are heated to melt. After that, the solder bumps 13 are cooled and solidified. This bonds the electrode pads 12 on the substrate 11 to the electrode pads 22 on the substrate 21 with the solder bumps 13 interposed therebetween.